International Journal of Scientific Engineering and Technology

Jagdeep Rahul ¹, Shekhar Yadav ², Vijay Kumar Bohat ²

Affiliations
1 VLSI Design Lab, Lovely Professional University, Phagwara, Punjab, IN
2 ABV Indian Institute of Information Technology and Management, Gwalior, M.P., IN

Abstract

In this paper, we propose a novel design analysis for a Junctionless Double Gate Vertical MOSFET (JLVMOS) with metal gate electrode and HfO₂, for which the simulations have been performed using TCAD (ATLAS), The simulated results exhibits significant improvements in comparison to conventional JLVMOS device with a polysilicon gate electrode and ITRS values for different node technology. In place of polysilicon gate and SiO₂ we have used metal gate and hafnium dioxide (HfO₂) respectively and observed that metal gate electrode with HfO₂ in JLVMOS shows drain current is 1.77mA, for a gate voltage of 1V and an average subthreshold swing, DIBL (Drain Induced Barrier Lowering) effect and leakage current are 61.01mV per decade, 40.4mV/V and 1.4nA/μm respectively. This significant improvement in drain current can be exploited for various low power high-performance circuit applications.

Keywords

DIBL, Junctionless Vertical Double Gate MOSFET (JLVMOS), DIBL (Drain Induced Barrier Lowering), Leakage Current (I_OFF), Subthreshold Swing (S. Swing), TCAD Tool.

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